Low-power technique of scan-based design for test - Electronics Letters

Introduction: The development of designs for test techniques continue to receive a great deal of consideration [l]. Techniques based on scan is one of the most effective methodologies and has been adopted widely in the area of digital integrated circuit design. When testing systems with scan design, the entire scan registers (SRs) andor combinational modules are always active during the whole scan shifting procedure. Because the power consumption introduced by the charging and discharging of load capacitances (switching power, Pd) is the main portion of a digital complementary metal-oxide-semiconductor (CMOS) circuit [2], power consumption of the digital system in the test mode is considerably higher than that in function mode [3].